The disclosures herein relate generally to amplifiers and more particularly to a system and apparatus for reducing offset voltages in folding amplifiers.
Complications can arise when designing analog-to-digital converters (ADCs) with reduced device area, low power consumption, and simple process flows. For example, to achieve relative high bit conversions while meeting performance criteria, improvements in resolution and speed can be achieved using various techniques that frequently result in increased area, power consumption, and circuit complexity. For example, to increase resolution from an 8-Bit converter to a 12-Bit converter, device size of associated circuits and devices such as resistor and capacitor networks must be increased to improve the accuracy 16xc3x97, for example, +/xe2x88x920.4% matching must be improved to +/xe2x88x920.024%. Increasing device size is commonly used but is undesired due to increased die costs associated with the overall increase in device size of the ADC to achieve a resolution and accuracy.
Another approach commonly used to reduce circuit mismatch is auto-zeroing errors that can be inherent to a specific circuit design. For example, comparator mismatching and shifts with time and temperature can produce errors in differential threshold levels. An auto-zeroing technique can be used that includes providing a capacitor to capture the analog voltage against which the input analog signal is compared and null the offset errors of the comparator. For example, at the beginning of each A/D conversion, analog capacitors of the A/D converter are connected to detect errors in their differential threshold levels and zero the errors accordingly. This technique requires an auto-zero time period followed by the comparison of analog voltage levels loading to increased circuit complexity and fabrication processes (i.e. double poly process) for creating zeroing capacitor modules.
Another conventional solution for reducing mismatch errors includes calibrating or trimming the ADC to offset the error created due to device mismatch. As previously stated, one source of error in ADCs is the mismatch of resistive and capacitive networks used to provide the basic elements of analog accuracy in an ADC. Device mismatch can be overcome through auto-calibrating the ADC to offset errors and includes adding and/or removing components to offset errors. For example, during a manufacturing process, resistors and/or capacitors can be manufactured in the same batch process to produce precision matched trimming components. Adding and removing components can then be accomplished by to trim the offset error. For example, during an A/D converter linearity test, resistors and/or capacitors can be connected and disconnected in small delta values with a laser trim, fusible links, programmable ROM or other technique to offset mismatch error. This technique is limited due to requiring initial and subsequent calibration in addition to increased circuit complexity, and additional processing to provide trimming devices and/or components.
Another auto-calibration technique includes digitally calibrating the ADC to offset errors produced due to variances from device performance resulting in device mismatch. For example, an ADC can include a calibration cycle and automatic temperature trimming by a precision resistor and capacitor network. During trim, various combinations of digital values are tried and matched against other combinations of bits. Detected errors are cancelled by switching components in and out to remove the error. A similar technique commonly used includes storing correction-value digital numbers that are added to, or subtracted from, subsequent conversion results. This technique can lead to errors during operation of the ADC based on variances in operating temperatures and/or device degradation of components. As such, an initial and/or recurring set-up for testing/trimming the ADC to offset errors can be needed to maintain accurate calibration data.
Therefore, a system and/or device is needed that provides accurate high resolution A/D conversion while minimizing device size, maintaining moderate circuit complexity, and fabricated using a pure digital CMOS fabrication process with minimal processing steps.